A prominent example for programmable phase-change memory cells having a plurality of programmable levels or states is Resistive Random Access Memory (“RRAM”), particularly phase change memory (“PCM”). PCM is a non-volatile solid-state memory technology that exploits the reversible, thermally-assisted switching of specific chalcogenides between certain states of different electrical conductivity.
PCM is a promising and advanced emerging non-volatile memory technology mainly due to its excellent features including low latency, high endurance, long retention and high scalability. PCM can be considered a candidate for Flash replacement, embedded/hybrid memory and storage-class memory. Key requirements for competitiveness of PCM technology can be multi-level cell functionality, in particular for low cost per bit and high-speed read/write operations, in particular for high bandwidth and high endurance. Multilevel functionality, i.e. multiple bits per PCM cell, can be a way to increase storage capacity and thereby to reduce cost.
Multi-level PCM is based on storing multiple resistance levels between a lowest (SET) and a highest (RESET) resistance value. Multiple resistance levels or levels correspond to partial-amorphous and partial-crystalline phase distributions of the PCM cell. Phase transformation, i.e. memory programming, can be enabled by Joule heating. In this regard, Joule heating can be controlled by a programming current or voltage pulse. Storing multiple resistance levels in a PCM cell is a challenging task.
For example, in “Phase-Change Memory”, it is described that the multiple states or levels in a PCM cell are created by varying the programming power, thus creating different crystalline and amorphous fractions within the cell. Further according to “Metal-oxide RRAM”, in metal-oxide resistive memory devices, multiple states can correspond to variations in the gap between conductive oxygen-vacancy filaments and the electrodes.
In resistive memory, the fundamental storage unit (referred to generally herein as the “cell”) can be set to a number of different states which exhibit different electrical resistance characteristics. Information is recorded by exploiting the different states to represent different data values. To read recorded data, cell-state is detected via measurements which exploit the differing resistance characteristics to differentiate between possible cell-states. A variety of semiconductor memory technologies employ these basic principles for data storage. Examples include oxide-based memory such as resistive RAM and memristor memory, ionic-transport-based memory, and PCM. The following will focus on PCM as a particularly promising technology for future non-volatile memory chips. It is to be understood however, that PCM is only an illustrative application for the invention to be described which can be similarly applied to other resistive memory technologies.
PCM exploits the reversible switching of certain chalcogenide materials between at least two states with different electrical resistance. In single-level cell (“SLC”) PCM devices, each cell can be set to one of two states, crystalline and amorphous, by application of heat. Each SLC cell can thus store one bit of binary information. However, to satisfy market demand for ever-larger memory capacity and reduce cost per bit, storage of more than one bit per cell is required. To achieve this, it is necessary that a cell can be set to s states where s>2, and that these states can be distinguished on readback via the cell resistance characteristics. Multi-level cell (“MLC”) operation has been proposed for PCM cells whereby each cell can be set to one of s>2 resistance levels, each corresponding to a different cell state. MLC operation is achieved by exploiting partially-amorphous states of the chalcogenide cell. Different cell states are set by varying the effective volume of the amorphous phase within the chalcogenide material. This in turn varies cell resistance.
To write data to a PCM cell, a voltage or current pulse is applied to the cell to heat the chalcogenide material to an appropriate temperature to induce the desired cell-state on cooling. By varying the amplitude of the voltage or current pulses, different cell-states can be achieved. Reading of PCM cells can be performed using the cell resistance to distinguish the different cell-states. The resistance measurement for a read operation is performed in the sub-threshold region of the current-versus-voltage (“IN”) characteristic of the cell, i.e. in the region below the threshold switching voltage at which a change in cell-state can occur. The read measurement can be performed in a variety of ways, but all techniques rely fundamentally on either voltage biasing and current sensing, or current biasing and voltage sensing. In a simple implementation of the current-sensing approach, the cell is biased at a certain constant voltage level and the resulting cell current is sensed to provide a current-based metric for cell-state. U.S. Pat. No. 7,426,134 B2 discloses one example of a current-sensing technique in which the bias voltage can be set to successive higher levels. The resulting cell-current compared to successive reference levels, for detecting the different cell-states. U.S. Pat. No. 7,542,338 B2 discloses a similar technique in which the cell current is simultaneously compared with different reference levels. In the alternative, voltage-sensing approach, a constant current is passed through the cell and the voltage developed across the cell is sensed to provide a voltage-based metric for cell-state.
For example, during RESET operation, the phase-change material in a PCM cell is heated above its melting temperature which is typically around 900 K. During SET operation, a temperature of typically about 450 K needs to be reached.
As the technology nodes progress towards 20 nm and beyond, the distance between two neighboring PCM cells becomes very small and very steep temperature gradients need to be reached to write one PCM cell without disturbing the other PCM cell.
A multitude of conventional solutions exist to avoid thermal disturb such as more thermally resistive materials between the neighboring PCM cells or deflection layers for thermal heat. But none of the conventional solutions alone can be sufficient to solve the thermal disturb problem. Additionally, some of the conventional solutions suffer from a trade-off between heat deflection and heat generation. When a deflection heat pathway is provided to lower the temperature at the neighboring PCM cell, the temperature in the written PCM cell is also lower so that the power consumption increases disadvantageously.
US 2013/0258767 A1 describes a PCM cell. A PCM cell includes a phase change material; a reference electrical terminal disposed on first side of the phase change material; first and second electrical terminals disposed on a second side of the phase change material; the phase-change material configured to be reversibly transformable between an amorphous phase and a crystalline phase, in response to a phase-altering electrical signal applied to the phase-change material via the reference electrical terminal and at least one of the first and second electrical terminals; a resistance measurement unit configured to measure a respective electrical resistance between each of the first and second electrical terminals and the reference electrical terminal; and a mathematical operation unit configured to determine a mathematical relation between the respective electrical resistances measured between each of the electrical terminals and the reference electrical terminal.
U.S. Pat. No. 6,791,102 B2 describes a method to manufacture a PCM. The PCM can include a phase change material having a bottom portion, a lateral portion, and a top portion. The PCM can further include a first electrode material contacting the bottom portion and the lateral portion of the phase change material and a second electrode material contacting the top portion of the phase change material.
WO 2010/038216 A1 describes PCM cells and fabrication thereof. A PCM cell includes two electrodes; PCM material and a dielectric barrier. The dielectric barrier is arranged to provide electron tunneling, e.g. Fowler-Nordheim tunneling, to the PCM memory material. A contact made of PCM material can also be provided. The dielectric barrier is substantially uniform e.g. of substantially uniform thickness, e.g. ≧5 nm.
U.S. Pat. No. 8,558,213 B2 describes a vertical PCM cell. A vertical PCM cell has an active region of PCM material defined either by providing a contact extending only over part of the PCM material or an insulating layer exposing only part of the PCM material. There can be more than one active region per cell allowing more than one bit of data to be stored in each cell.
U.S. Pat. No. 8,624,236 B2 describes a PCM cell having vertical channel access transistor. A device includes a substrate having a first region and a second region. The first region includes a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.
U.S. Pat. No. 8,486,745 B2 describes multi-terminal phase change devices. Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.
In “Enhanced Thermal Efficiency in Phase Change Memory Cell by Double GST Thermally Confined Structure”, an enhanced thermal efficiency in PCM cell by double GST thermally confined structure is described.
Accordingly, it is an aspect of the present invention to provide an improved memory device including a plurality of PCM cells.